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TSMC's N2 process has a major advantage over Intel's 18A: SRAM density
By contrast, TSMC's N2 manufacturing technology shrinks HD SRAM bit cell size to around 0.0175 µm^2, enabling SRAM density of 38 Mb/mm^2. Both 18A and N2 rely on gate-all-around (GAA) transistors ...
Semiconductor Engineering8d
Impact of Extremely Low Temperatures On The 5nm SRAM Array Size and Performance
A new technical paper titled “Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures” was published by ...
Design-Reuse23d
MoSys 1T-SRAM Macros Now Proven in Multiple Versions of TSMC'S Standard and Triple-Oxide 0.13-Micron Logic Processes
MoSys 1T-SRAM Macros Now Proven in Multiple Versions of TSMC'S Standard and Triple-Oxide 0.13-Micron ... The single transistor bit cell used in 1T-SRAM technology results in the technology achieving ...