TSMC continues to expand its 5nm technology family to meet diverse customer demands. These include N5P, N4, and N4P for better power, performance and density, N4X, a process tailored for high performance computing (HPC) applications, and N5A for automotive applications.

In December 2021, TSMC announced a new member of its "5 nm" process family designed for HPC applications: N4X. The process featured optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors.

A leading edge 5nm CMOS platform technology has been defined and optimized for mobile and HPC applications. This industry-leading 5nm technology features, for the first time, full-fledged EUV, and high mobility channel (HMC) finFETs with densest 0.021μm 2 HD SRAM.

Jun 25, 2022 · Angstronomics presents the hard truths of the world's most advanced process node. We detail their claims vs real chips, how transistor density is calculated, show concrete measurements on the real dimensions of TSMC N5, and get technical on its transistor layout to explain area scaling.

Jun 24, 2019 · TSMC’s 5nm technology is 15% faster with 30% lower power than 7nm. A second version of 5nm, due out next year, is 7% faster. Both versions also will use EUV. TSMC is gaining some traction for 5nm. “Apple, HiSilicon and Qualcomm are expected to be in high volume at 5nm in 2020,” said Handel Jones, chief executive of International Business ...

Fully-fledged EUV replaces at least four times more immersion layers at cut, contact, via and metal line masking steps for faster cycle time, better reliability and yield.

Aug 25, 2020 · TSMC's 26th Technology Symposium kicked off today with details around its progress with its 7nm N7 process, 5nm N5, N4, and 3nm N3 nodes. TSMC also shared details around its 3DFabric...

Apr 5, 2019 · TSMC announced they've completed the infrastructure design for the 5 nm process, which is the next step in silicon evolution when it comes to density and performance.

TSMC’s comprehensive 5nm design infrastructure includes the full versions of the 5nm Design Rule Manual (DRM), SPICE model, process design kits (PDKs) and silicon-validated foundation and interface IP, and also supports a full range of certified EDA tools and design flows.

underway in 5nm • Designing in FinFET brings many challenges including simulation complexity and runtime; need to pay close attention to parasitics, proximity and matching, and balance accuracy and design time • 5nm is significantly more complex than 16nm/12nm, but no new techniques are needed; our PLL circuit topology